The present invention relates to the packaging of integrated circuits. Some specific embodiments of the invention pertain to an integrated circuit (IC) package that has a metal substrate and a flexible thin film interconnect structure upon which the IC is mounted and a method for manufacturing the same.
The semiconductor industry continues to produce integrated circuits of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has in turn resulted in an increased number of input/output pads on the circuit chips. At the same time, the increased density of the chips has driven the input/output pad pitch downward. The combination of these two trends has been a significant increase in the connector pin wiring density needed to connect the chips to packages that interface with the outside world and/or interconnect the chips to other integrated circuit devices.
One technology that has been used to meet such high density packaging demands combines flip chip and ball grid array (BGA) technologies to produce relatively small chip scale packages that have a relatively high lead count. According to one conventional method for creating flip chip BGA packages (FCBGA), a thin film interconnect structure is formed over one side of a laminate substrate, such as a printed circuit board (PCB), that has through holes that provide electrical connections from one side of the substrate to the other. A plurality of high density flip chip bonding pads are formed in the thin film interconnect structure and solder bumps are affixed to an integrated circuit which is then flipped upside down such that the solder bumps are brought into contact with their corresponding high density bonding pads. The solder balls are then reflowed to connect the integrated circuit to the thin film side of the PCB substrate.
Underfill, such as a thermo-set epoxy, is then dispensed in the gap between the integrated circuit and the substrate. The underfill is then cured by heating the substrate and integrated circuit to an appropriate curing temperature. Next, the assembly is cooled down and solder balls are attached to BGA bonding pads formed on the other side of the substrate to complete the packaging structure. Circuits connecting the BGA pads on the one side of the substrate to the high density flip chip pads (and therefore to the attached die) on the other side of the substrate are made through the plated through holes.
In order to achieve the high density interconnections desirable for some integrated circuit die packaging solutions, accurate registration of the photolithography involved in the formation of the thin film interconnect structure is critical. One problem with this conventional approach is that the laminate substrate over which the thin film layers are formed is subject to slight mechanical changes when subjected to humidity, different temperatures and other environmental factors. These slight mechanical changes may interfere with the accuracy of the thin film photolithography process thereby resulting in defective packaging structures.
NEC has researched and developed FCBGA technology that uses a metal substrate base instead of the traditional PCB laminate base. Using a metal substrate provides better registration accuracy than a traditional PCB or other type of laminate substrate which in turn enables very high density patterning steps to be more accurately used in the thin film interconnect structure formed over the substrate. According to NEC, their technology also is more cost effective than previously employed FCBGA technologies as fewer layers are fabricated and a smaller number of the fabricated layers need to be fine-pitch patterned.
FIGS. 1A–1G are simplified cross-sectional views of a packaging structure formed according to a first metal-substrate FCBGA process developed by NEC. This first NEC process forms a thin film interconnect structure over a metal substrate 10 of which only a portion is shown in FIGS. 1A–1G. The NEC engineers noted that substrate 10, which may be a stainless steel and copper alloy, should be an easily obtainable material that is suitable for manufacturing to high-tolerance flatness while also being strong enough to resist the pressure toward curvature that is exerted by a resin-film structure formed over the substrate.
As shown in FIG. 1A, the NEC process starts by forming a plurality of BGA pads 12 over metal substrate 10. BGA pads 12 are a three layer stack of gold (12a), nickel (12b) and copper (12c) as shown in FIG. 1B. Next, a thin film interconnect structure 14 is formed over the BGA pads (FIG. 1C). Interconnect structure 14 may include several thin film dielectric layers 16a, 16b and 16c as well as several thin film conductive layers 18a, 18b. Vias 20 interconnect various portions of layers 18a and 18b to each other and to BGA pads 12. Also formed on the upper surface of the thin film interconnect structure 14 are a plurality of flip chip pads 22 that enable bonding of an integrated circuit die 30 as shown in FIG. 1D.
IC die 30, of which only a portion is shown in FIGS. 1D–1G is attached to pads 22 using solder bumps 36. An underfill layer 34 is applied between the bottom of IC 30 and the top of thin film interconnect structure 14 in order to reduce the stress and fatigue on the solder balls during thermal cycling.
Referring to FIG. 1E, next a stiffener 38 and a lid 40 are added. In order for stiffener 38 to be adequately secured to the thin film interconnect structure 14 formed over substrate 10, a conductive adhesive (not shown) is applied between the stiffener and thin film structure at interface 39. Also, a thermal grease 42 may be placed over integrated circuit 30 before lid 40 is attached. After stiffener 38 and lid 40 are attached, metal substrate 10 is removed using a wet etch process to expose the BGA pads 12 as shown in FIG. 1F. Finally, the structure may be completed by attaching a heat spreader (not shown) to lid 40 and forming BGA solder balls 44 (shown in FIG. 1G) on pads 12 as appropriate.
FIGS. 2A and 2B are top and bottom perspective views, respectively, of the completed structure. For ease of illustration, a portion of lid 40 has been removed (shown in dotted lines) exposing integrated circuit die 30 and portions of stiffener 38. As shown in FIG. 2A, the packaging structure includes a central opening 50 in which die 30 is positioned. Also, the bottom surface of the structure includes a plurality of equally spaced solder balls 44 spaced apart from each other at an appropriate BGA-pitch.
While the above described process seems to be an improvement as compared to the conventional FCBGA technology described above. It suffers from a number of drawbacks. First, integrated circuit 30 is attached to thin film interconnect structure 14 before the thin film structure can be adequately tested for shorts using conventional electrical testing techniques, e.g., contact testing. This is because IC die 30 is attached prior to removing metal substrate 10 by the wet etch process. Forming thin film interconnect structure 14 over a conductive substrate, such as metal substrate 10, shorts the various circuits formed in the interconnect structure until the conductive substrate is removed. Thus, if a short or similar defect exists in thin film structure 14, integrated circuit 30, which may be quite expensive, may be lost resulting in a lower yield process unless specialized optical or other testing techniques are employed.
Another drawback with the above-described NEC approach is that it would most likely require that the ground reference plane for the interconnect package be formed in the relatively expensive thin film structure. While it is possible to use a metal stiffener 38 as the ground reference plane, all conductive adhesives known to the present inventors that may be used to attach the stiffener to thin film structure 14 would act as a high ohmic reference plane that would have a resistivity at least one or two orders of magnitude higher than copper. This approach would thus greatly slow down signals passing through the interconnect structure making it impractical for high speed devices.
NEC solved some of the above-noted problems when it developed technology described in U.S. Patent Application 2002/0001937 A1, which was published on Jan. 3, 2002 (hereinafter the “'1937 application”). A number of different processes for forming a semiconductor package board are described in the '1937 application. Each of these different processes uses a metal substrate similar to substrate 10 as a base for an overlying thin film interconnect structure. The interconnect structure includes a plurality of metal interconnect pads that are formed directly on the metal substrate. A central opening in the substrate is subsequently formed that exposes these metal interconnect pads for attachment to an integrated circuit that can be positioned within the central opening.
FIGS. 3A–3D are simplified cross-sectional views of a packaging structure formed according to one of the techniques described in the NEC '1937 application. Referring to FIG. 3A, the process starts by providing a metal substrate 60, which unlike the previously described NEC process, will become part of the final packaging product. A first set of bonding pads 62 is formed directly on substrate 60 and, as shown in FIG. 3B, a thin film interconnect structure 65 is formed over the substrate and over bonding pads 62.
Thin film interconnect structure 65 may include plural metal signal lines 64 separated by respective dielectric layers 63. A second set of bonding pads 66 is then formed over the top dielectric layer of thin film interconnect structure 64. The first set of bonding pads are ultimately connected to an integrated circuit die while the second set allow the die to be connected to the outside world through, for example, a BGA structure. Thus, second set of bonding pads 66 has a pitch that is greater than the pitch of first set of bonding pads 62.
Referring to FIG. 3C, a protective layer of photoresist 68 is then applied over the upper and lower surfaces of the structure and patterned on the lower surface to expose a central opening 70 of metal substrate 60 that is to be etched away. After a portion of substrate 60 is etched away to expose bonding pads 62, an integrated circuit die 72 can be positioned within opening 70 and connected to the first set of bonding pads as shown in FIG. 3D. A filler material such as filler 74 fills the space between die 72 and the packaging structure. Finally, BGA solder balls 76 are mounted to pads 66 formed on the upper surface of the structure.
FIGS. 4A and 4B show top and bottom perspective views, respectively, of the final packaging structure. As can be seen from a comparison of FIGS. 4A and 4B to FIGS. 2A and 2B, the final structure formed using this technique is very similar to the final structure formed from the earlier-described NEC technique even though the processes used to produce these structure are in themselves very different.
While the above described technique provides some improvement over the earlier described NEC technique, including the capability to test for short circuits prior to attaching a die, it is not without its own limitations. For example, while there are many different embodiments or variations of the above described technique set forth in the '1937 application, one element that each embodiment has in common is that the first set of bonding pads 62 (e.g., the flip chip pads) are formed directly on the surface of the metal substrate 60. This prevents forming signal lines in areas of the packaging structure outside the region designated for central opening 70 concurrent with the formation of pads 62 because any such signal lines formed directly on metal substrate 60 would be shorted together. Also, the etch step that removes metal substrate 60 in opening 70 may tend to undesirably etch pads 62 under some conditions. Additionally, the vertical sidewalls of pads 62 create areas of stress at corner regions 78 (shown in FIG. 3A) that may result in reliability problems under certain conditions.
Thus, while each of the NEC metal-substrate FCBGA processes described above represent improvements in some respects over previously known laminate-substrate FCBGA techniques, new and improved integrated circuit packaging techniques and structures are desirable.